Embodiments of the present invention relate to the field of performing diagnostics and testing on integrated circuits and, in particular, to integrated logic structures for creating events that can be used to feed integrated hardware registers.
Some integrated circuits (ICs) include registers or counters that can be used to store results of diagnostic or performance tests. The counters can also be used to monitor specific hardware events in the IC. The counters are used by internal processes and by externally driven processes. Counter values can be accessed by external devices through communications buses, such as a configuration bus or a debug bus, used in some ICs. A configuration bus is used for programming the chip during normal operation. For example, a CPU (Central Processing Unit) can initiate cycles which read or write registers in an MCH (Memory Controller Hub). A debug bus is used for observing internal logic for debug purposes.
In order to feed values to the counters, a unit within the IC is designed with all the necessary logic at the source of the signals that are to be tested for that unit. The logic at each unit is specifically designed for its unit to perform functions believed to be important at the time that the unit is designed. In a conventional implementation, the logic is activated by an external or internal trigger event. It performs the function for which it is designed and the result is fed as an event indication to a counter or register. This register can be read using the chip's configuration bus or the register can be observed using the debug bus.
Logic gates are accordingly added to the IC for each event that is to be monitored. This can significantly add to the gate count of the system, while at the same time, the specific logic design limits flexibility as it is typically hard-coded as firmware.
The integral logic at each unit also limits the tests to those that are developed during the circuit's initial design. Any tests that are developed after tape out cannot be performed. The requirement to provide for all necessary tests in advance can also slow development of the IC while time is spent thinking of possible bugs and events for test. The diagnostic logic, because it is located at the source of a signal is further not well adapted to test combinations of signals that are generated by different units of the IC.